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The way to distinguish whether the memory cell is storing "1" or "0" information (read operation) is by a circuit called a sense amplifier. A sense amplifier, which is described in detail in Section 7.4.3, is basically a cross-coupled latch that detects a small voltage difference between the detected node and the reference node. Since the sense amplifier circuit takes up a large area compared to a memory cell, only one sense amplifier is provided for a large number of memory cells, usually for 128 or 256 memory bits. All the memory cells connected to a common sense amplifier share a common bit line as illustrated in Figure 7.7. The memory access is such that only one word line is activated among a 1the memory cells connected to a common bit line. The sensing proceeds as follows. Be-ore a word line is activated to access a memory cell, the bit line pairs (BL and Br) are precharged to a same voltage, usually VDD/ 2 . At this point, the memory cell capacitor is isolated from the bit line since the access transistor is off. Assume that the memory cell stores "1" state, or voltage, VDD. After the word line is activated and the access transistor turns on, the memory cell capacitor becomes connected to the bit line. Denoting the memory cell capacitance as Cs and the total bit line capacitance as CB, the resulting bit line voltage rises above VDD/2 by

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